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Table 1-10:
Detailed Description
Expansion I/O Single-Ended Connections (J6) (Continued)
J6 Pin
56
58
60
62
64
Schematic Net Name
HDR1_56
HDR1_58
HDR1_60
HDR1_62
HDR1_64
FPGA Pin
Y26
P26
AA25
AC26
AB26
Other Expansion I/O Connectors
In addition to the high-speed I/O paths, additional I/O signals and power connections are
available to support expansion cards plugged into the ML501 board. Fourteen I/O pins
from the general-purpose pushbutton switches and LEDs on the board are connected to
expansion connector J5. This permits additional I/Os to connect to the expansion
connector if the pushbutton switches and LEDs are not used. The connection also allows
the expansion card to utilize the pushbutton switches and LEDs on the board.
The expansion connector also allows the board's JTAG chain to be extended onto the
expansion card by setting jumper J21 accordingly.
The IIC bus on the board is also extended onto the expansion connector to allow additional
IIC devices to be bused together. If the expansion IIC bus is to be utilized, the user must
have the IIC pull-up resistors present on the expansion card. Bidirectional level shifting
transistors allow the expansion card to utilize 2.5V to 5V signaling on the IIC bus.
Power supply connections to the expansion connectors provide ground, 2.5V, 3.3V, and 5V
power pins. If the expansion card draws significant power from the ML501 board, ensure
that the total power draw can be supplied by the board.
The ML501 expansion connector is backward compatible with the expansion connectors
on the ML40 x , ML32 x , and ML42 x boards, thereby allowing their daughter cards to be
used with the ML501 Evaluation Platform. Table 1-11, page 24 summarizes the additional
expansion I/O connections.
ML501 Evaluation Platform
UG226 (v1.4) August 24, 2009
www.xilinx.com
23
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